Principal Engineer, AI & ML Design Verification (AI2517)
San Jose · Full time · Posted 4MO AGO
Job Title: Principal Engineer, AI & ML Design Verification Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office) Job ID: AI2517 Description: The Design Verification (DV) team at SiMa is involved in the functional verification of Machine Learning Accelerator (MLA) and data processing at block, sub-system and SoC. As well involved in bring-up and debugging on emulators and silicon.In addition, this job role requires development, enhancement and on-going support and maintenance of MLA Test Bench and Test Cases for SiMa ML IP. Job Description As the experienced MLA Design Verification Engineer, you will
- Independently perform MLA verification execution and closure.
- Participate in MLA architecture, micro-architecture and feature discussions and reviews.
- Define and develop MLA test bench components using UVM & System Verilog.
- Develop and execute a test plans.
- Lead Code coverage reviews and closure. System Verilog Assertion functional coverage development and closure.
- Manage debugging of test and regression failures.
- Help emulation team with triaging failures.
- Work closely with the Architecture, SoC Hardware and Software teams.
- BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 12+ years of experience in functional verification of pipe-line based design preferably MLAs, DSPs, CPUs or GPUs.
- Very good experience of UVM and System Verilog based verification methodology is a must.
- Good working experience of development of UVM and System Verilog Test Bench (BFMs, ScoreBoards, SVA etc..) from scratch along with usage know how of debug & coverage tools.
- Skill set for silicon debug on the lab/board set-up is a plus.
- Good debug, coding and problem solving skills.
- Knowledge of AMBA protocols is a must.
- Formal/SVA knowledge is a plus.
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