Example Company
Software engineer
- Location
- San Francisco
- Type
- Full time
- Compensation
- $150k-$200k
- Posted
- 2 days ago
Join a team building useful software. Work closely with engineering and design to turn new ideas into products.
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STA Engineer
- Location
- Bengaluru
- Posted
- 7D AGO
About the role
CScale is building the interconnect for gigawatt-scale AI. As AI scale-up moves toward deployments spanning thousands of accelerators and dozens of racks, the network needs to deliver high bandwidth, predictable low latency, and continuous communication. CScale is building integrated optical interconnect designed for this new scale, enabling accelerators to work together like a single, much larger computer. But at this scale, performance is only part of the challenge. Optical failures are inevitable, and the system needs to keep running. CScale is designing the interconnect for continuity. Lasers will fail. Compute shouldn’t. The ambition is simple: Build AI interconnect you can take for granted. CScale came out of stealth in September 2026 with $145 million in Series C funding, bringing total funding to $188 million.
Key Responsibilities:
- Develop the SYNTH & STA flow using PrimeTime/Tempus.
- Develop and validate timing constraints (SDC) for functional and test modes (DFT, scan, MBIST).
- Run Top-Level/Sub-System/Block level timing analysis and drive designs to timing closure.
- Debug setup and hold violations, and work with Physical Design and Design teams to fix them.
- Generate, implement and validate timing ECOs, and confirm each fix holds across all modes and corners.
- Produce and review timing reports across modes and corners, and flag risks and trends to the team.
- Support timing signoff, and root-cause timing and constraint issues through tape-out.
Requirements:
- 8-12 years of hands-on experience in SYNTH, STA, constraint development & validation, timing signoff and ECO implementation.
- Strong grasp of timing fundamentals, including setup/hold checks, clock definitions, SDC constraints and timing exceptions.
- Practical experience with industry-standard STA tools (Synopsys PrimeTime or Cadence Tempus).
- Understanding of the physical design flow (placement, clock tree synthesis, routing) and its impact on timing.
- Exposure to timing analysis across multiple modes and corners (MMMC).
- Proficiency in Tcl, Perl or Python for automation and report analysis.
- Strong analytical and debugging skills.
- Proven ability to work across Physical Design, RTL, DFT and constraints teams.
- Excellent communication and problem-solving skills.
- Experience with advanced process nodes is a plus.
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