Example Company
Software engineer
- Location
- San Francisco
- Type
- Full time
- Compensation
- $150k-$200k
- Posted
- 2 days ago
Join a team building useful software. Work closely with engineering and design to turn new ideas into products.
Loading job details
Junior DV and FPGA Prototyping Engineer
- Location
- Remote
- Posted
- 19D AGO
About the role
Country: Ukraine
Brand: Capgemini Engineering
Reference: 379597-en_GB
Contract type: Permanent
Experience level: Experienced Professionals
Professional community: Software Engineering
Business unit: Engineering and RandD Services
At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.
Your Role
Your on-job tasks would consist of:
- Studying AMD Vivado and Vitis IDE
- Modelling (Python) and RTL implementation (System Verilog) of the proposed image and/or audio processing algorithms
- Building FPGA environment and debug of the implemented RTL design using Zybo Z7 board
- Building SV based verification environment for simple RTL designs like FIFO, UART.
We’d expect you to learn:
o OOP concepts in System Verilog (classes, inheritance, polymorphism)
o Constrained randomization (rand variables, constraints, inline constraints, conflict solving)
o Functional coverage (covergroups, coverpoints, cross coverage, bins)
o Assertions (simple SVA properties checks)
- Studying UVM methodology
- Wrapping SV based environment into UVM
- Shell and Python scripting
Mandatory qualifications
- Bachelor’s/Master’s Degree in Electronics or related fields
- Good understanding of digital logic design basics
- Basics of IC design & verification using System Verilog
- Beginner’s experience with EDA tools (AMD Vivado (Xilinx), Intel Quartus (Altera), Cadence, Synopsys or similar)
- Understanding OOP concepts
- Beginner’s level of English or higher
Optional qualifications you may have
- FPGA design using HDL (Verilog, VHDL) or schematics editor
- CPU architecture knowledge, embedded SW development
- Scripting using Bash, Python, TCL etc.
Capgemini is a global business and technology transformation partner, helping organizations to accelerate their dual transition to a digital and sustainable world, while creating tangible impact for enterprises and society. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, generative AI, cloud and data, combined with its deep industry expertise and partner ecosystem.
#LI-ID3
#LI-Remote
Similar roles
Senior Software Engineer, Backend (ML Training and Serving)Affirm · Remote
Full Stack EngineerGitar- Senior General/Interdisciplinary EngineerOdyssey
Software Principal Engineer- System Test, Hardware & Firmware Validation (SONiC AI & Enterprise Networking)Dell Technologies · Bengaluru · Chennai
Forward Deployed Construction Engineer (Belgium)Brickanta · Brussels · Remote
Software Engineer (Platform/Backend) - UEM Reporting PipelineOmnissa · Atlanta · Remote