CScale is building the interconnect for gigawatt-scale AI. As AI scale-up moves toward deployments spanning thousands of accelerators and dozens of racks, the network needs to deliver high bandwidth, predictable low latency, and continuous communication. CScale is building integrated optical interconnect designed for this new scale, enabling accelerators to work together like a single, much larger computer. But at this scale, performance is only part of the challenge. Optical failures are inevitable, and the system needs to keep running. CScale is designing the interconnect for continuity. Lasers will fail. Compute shouldn’t. The ambition is simple: Build AI interconnect you can take for granted. CScale came out of stealth in September 2026 with $145 million in Series C funding, bringing total funding to $188 million.

The Role

You will own the physical design of our optical engine packages — redistribution layers, substrate, and the bump and ball maps that tie the die stack to the host board. This is a hands-on layout role with real architectural influence.

You will work between our PIC and EIC design teams, our SI/PI and thermal engineers, and our supply chain (wafer fab, substrate vendor, OSAT). You will not be handed a finished floorplan to route — you will help define it.

What You'll Do

Layout execution

• Deliver RDL/UBM and package substrate layouts for our optical engine products and test vehicles, from floorplan through tape-out.
• Define and release bump maps, ball maps, and escape routing strategies for multi-die assemblies (PIC, EIC, and light source die).
• Design to 200G/lane-class electrical requirements: differential pair routing, reference-plane integrity, crosstalk isolation, and power delivery for high-current, low-noise rails.

Co-design and floor planning

• Participate from concept phase: produce preliminary floorplans and stack-up proposals that reconcile electrical, optical, thermal, and mechanical constraints before they are frozen.
• Iterate with SI/PI engineers on test routes to converge routing topologies and design rules.

Design rules, DFM, and supplier engagement

• Work directly with wafer fabs, substrate suppliers, and OSATs to capture and negotiate design rules, stack-ups, and assembly constraints.
• Generate fab and assembly release packages; drive DFM/DFA closure and design reviews through to sign-off.
• Flag rule conflicts early and propose alternatives rather than routing around them silently.

Verification and automation

• Run and own physical verification: DRC, connectivity/LVS-style netlist checks, and cross-domain consistency between die, package, substrate, and board.
• Manage netlists for heterogeneous assemblies across revisions and product variants.
• Build scripted automation (SKILL, Python, or equivalent) for repetitive layout, checking, and release tasks.

Build support

• Support test vehicle definition, first builds, bring-up, failure analysis, and yield learning — including layout changes driven by assembly reality.

Required Qualifications

• BS or MS in Electrical Engineering, or equivalent practical background.
• 6+ years of IC package physical design, including at least one product taken from concept through tape-out and volume-relevant build.
• Expert-level proficiency in a package layout tool: Cadence Allegro Package Designer / APD+ / SiP, Siemens Xpedition Package Designer, Synopsys IC Package, or equivalent.
• Demonstrated experience with multi die packaging: 2D or 2.5/3D integration.
• Working fluency with multi-layer organic substrate construction and how material and stack-up choices constrain routing.
• Practical experience closing DFM/DFA with external substrate suppliers and OSATs.
• Comfortable working in English across a distributed team and multiple time zones.

Preferred Qualifications

• Demonstrated experience with advanced packaging: 2.5D/3D integration, RDL, TSV interposers, fan-out, microbump or Cu-pillar flip-chip.
• Layout for 112G/224G SerDes or comparable high-speed interfaces; familiarity with signal and power integrity workflows (e.g. Cadence Sigrity/PowerSI, Ansys).
• Familiarity with mask and RDL vendor flows, GDS-based layout environments (Virtuoso, KLayout), and AutoCAD file exchange.
• Experience with package/IC co-design environments (e.g. Cadence Integrity 3D-IC).
• Scripting for design automation and rule checking.
• Experience at a startup or on a first-of-its-kind product, where the design rules did not exist yet.

Why This Role Is Different

Most package layout roles are a step in someone else's flow. Here, the package is the product. You will be one of a handful of people who determine whether a next-generation optical engine is manufacturable, and you will see your layout decisions land in silicon and in an OSAT line within months, not years.