ADVANCE YOUR CAREER. ADVANCE THE WORLD. 

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. 

 

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

As a Signal Integrity Engineer at Adaptive and Embedded Computing Group (AECG), AMD, you will be responsible for ensuring that AMD’s next-generation products deliver industry-leading reliability, performance, and efficiency. This role involves analyzing, modeling and validating the complex interconnects of high-speed Serializer/De-serializer (SerDes) channels @56/64/112/128/224+ Gbps, High speed memories like LPDDR4/5x/6, DDR5, PCIe Gen 5/6 etc., and 400/800/1600Gbps Ethernet links. You will be providing guidelines to board layout teams based on SI and Power simulations and for high-speed structures.

 

THE PERSON:

In this role, you will closely collaborate with Board HW designers, HW architects, IC packaging team, PCB team, and external partners/suppliers to ensure first time success of the system/board products.

 

KEY RESPONSIBILITIES:

• Model and simulate the end-to-end high-speed channels including transceivers, IC package, PCB and cross-boards connectors/cables
• Utilize industry-standard tools and methodologies to perform a variety of time/frequency domain signal integrity analysis (IBIS-AMI, SPICE, full-wave EM analysis, etc)
• Identify the link quality such as loss, reflection and crosstalk, and resolve the issues
• Conduct channel-simulations to optimize Eye Diagram, Bit Error Rate (BER) and Signal-Noise-Ratio (SNR) for high-speed signaling in a complex system.
• Interpret the simulation results to provide the design guidelines on board materials, stack-up, transmission line routings, component placement and layout optimization
• Review PCB layout and board material/stack-up, identify the potential signal integrity and power integrity issues, and propose the solutions
• Support lab validation and debugging to correlate with the simulation data
• Collaborate with cross-functional teams to drive product development while keeping projects on schedule and within scope.

 

PREFERRED EXPERIENCE:

• Strong experience in high-speed signal integrity engineering
• Proficiency in SI simulation tools (Keysight ADS, Cadence Sigrity, Ansys HFSS)
• Strong expertise in high-speed architecture, interconnects and PCB/package design
• Knowledge of high-speed interfaces (PCIe, Ethernet, DDR, etc.)
• Familiarity with MATLAB or Python for data analysis and automation
• Hands-on experience with lab testing tools (TDR, VNA, high-speed oscilloscopes)
• Excellent problem-solving and cross-functional collaboration skills

 

ACADEMIC CREDENTIALS:

• Masters or PhD degree in Electrical Engineering, Computer Engineering, or related field 

 

This role is not eligible for visa sponsorship.

 

#LI-TB1

 

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.