Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As engineers within the CPU team and as leads of CPU units (fetch, decode/rename, scalar execute, fp/vector execute, load/store, memory management/TLB, prefetching, debug/trace, system/IO, and multi-level cache subsystem), you will be writing specifications and developing RTL for the CPU which targets and delivers industry leading power, performance, and area.

THE ROLE

As a CPU Micro-Architect/RTL Engineer, you will participate in the following:

• Micro-architecture development and specification - starting from a performance driven design strategy, you will work with our performance modeling team and study early micro-architectures and converge on a design captured in a detailed specification.  Critical understanding of the various pipelines and intra-unit communication will be necessary to build a clean yet performant design.

• RTL design - develop and refine RTL which targets the power, performance, area and timing goals.  A solid understanding of the modern Verilog standards is a plus, enabling you to write RTL which is flexible and robust, configurable, and scalable.

• Verification - assist the verification team in all forms of CPU verification used, such as testbench development, formal methods, and simulation/emulation for formal verification

• Performance exploration and correlation - explore high-performance strategies and work with the performance architecture and verification team to verify that the RTL meets targeted performance.  

• Physical design - work with the PD engineering team to implement and verify the physical design meets the goals.  Be able to iterate and refine the RTL design.  Incorporate improvements for timing, power, area, DFT, and reliability. 

REQUIREMENTS — MUST TO HAVE

• BS or MS with 15+ (leads) and 7+ (ICs) years experience in high-performance, low-power CPU design

• Experience with coding in Verilog, debugging, simulation, ideally with experience driving modern AI Tools to assist in RTL coding

• Solid understanding of logic and physical design and the impacts on timing, power, and area

• Experience with RISC-V or ARM64 or x86 ISA and their impacts on CPU micro-architectural choices

REQUIREMENTS — NICE TO HAVE

• Expertise in one or more of the following areas: instruction fetch, branch prediction; instruction decoding, scheduling and register renaming; out-of-order execution; integer and floating point execution; load/store execution; prefetching; cache and memory subsystems; translation and memory management; memory coherence and ordering; power and thermal management; and clocking / reset design

• Strong background in low power microarchitecture and high-performance design techniques, with a proven track record of execution on multiple CPU programs and products

• Experience in C, C++, and other languages such as Perl or Python