Overview / Job Summary :

We are looking for top-notch engineers to join our global team. If you’re interested in being a part of our journey and helping us grow to become the leading provider of SoC platform solutions, we want to hear from you.

We need you to implement and help improve the digital blocks in analog-on-top products. These products are motion sensors made of state-of-the-art MEMS combined with ASIC and proprietary algorithms and firmware, addressing Consumer, Industrial and Automotive markets. You will be a key player of the RTL to GDS process, and you will also be collaborating with the relevant upstream and downstream teams in an international environment.

Job Description :

• Generate of block level timing constraints working with RTL and DFT teams.

• Run Logical/Physical synthesis, Formal Verification, develop and validate clock network guidelines.

• Interface with Physical-Design team for driving block closure.

• Generate/promote constraints and setting up of proper methodologies for chip level timing closure of Analog-Mixed-Signal designs.

• Run Static Timing Analysis (STA) at block and chip level, provide guidelines for STA-Signoff closure to Design and Physical-Design teams as well as generating ECO fixes and driving ECO loops.

• Develop and maintain methodologies and flows.

Qualifications

• The ideal candidate will have 5+ years of hands-on experience in Synthesis and Timing closure (STA) with Signal-Integrity analysis, OCV, and Multi-Mode-Multi-Corner (MMMC)

• Solid experience in developing and implementing timing constraints and strong understanding of all aspects of timing closure of various functional and test modes such as scan shift/capture and BIST/Memory-BIST

• Familiarity with HDL languages like Verilog and Physical Implementation aspects for proficiently interfacing with RTL and Physical design teams for constraints development and timing closure

• Knowledge of low power design implementation using UPF/CPF

• Good knowledge of usual design structure such as clock gating/divider structure , synchronization mechanisms

• Knowledge of timing constraints for standard interfaces I2C/SPI/I3C

• Proficient in usage of industry standard Synthesis, Formal Verification, STA tools (Synopsys tool suite)

• Deep understanding of scripting languages such as Tcl/Perl/CShell

• Experience/Knowledge of DFT and ATPG will be a plus.

• Excellent verbal and written communication skills are required.

• Excellent interpersonal and analytical skills with the ability to work with other team members to resolve issues and targeting critical cases.

• Highly motivated, excellent team spirit, product oriented.

• Education: Minimum B.S. - Any Specialization, Electronics/Telecommunication, Electrical

Candidates with less experience but strong motivation and growth potential might be considered.

InvenSense, a TDK group company, is a world-leading provider of MEMS and magnetic sensor solutions found in mobile, wearable, smart home, AR/VR, and other consumer and IoT applications. We are innovators with a 20+ year history of patented sensor technologies. As experts in our field, we lead industry breakthroughs in consumer, industrial and automotive technology and reliably deliver high-quality solutions to our partners across global markets. 

Learn more about us at invensense.tdk.com

Contact: Anne-Laure.Mareau@tdk.com