Number of Position(s): 2
Duration: 4+ months
Dates: January 2027 - May 2027 
Location: Onsite in San Jose, CA

Educational Requirements

Currently a candidate for a master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field with an accredited school in the US.
 

• Familiarity with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc.
• Familiarity with analog / mixed signal IPs or chips in deep submicron CMOS technologies.
• Good understanding of device physics and the impacts of layout effects;
• Familiarity with behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS
   

• Design, implement, and simulate the functionality and performance of various high speed analog circuits, including the ADCs and DACs
• Create the layout floor plans to optimize the overall performance
• Exploring the trade-offs of the different circuit topologies