About the job

As a Resolution Enhancement Techniques (RET) OPC Verification Engineer, you'll architect new TI products and make our customers' visions a reality. You'll define, design, model, implement, and document analog, digital, and RF integrated circuits (ICs). Responsibilities will include, but are not limited to: 

• Working with designers and fab engineers to understand lithography requirements for RET.
• Translating lithography requirements into an implementation plan for OPC Verification-recipe code.
• Writing OPCV-recipe code.
• Optimizing OPCV-recipe parameters for hotspot prediction and minimizing false errors.
• Creating test cases for OPCV-recipe code.
• Reviewing large RET-output layouts for quality.
• Interfacing with lithography and yield enhancement teams.

Minimum requirements:

• Master’s degree in Electrical Engineering, Physics, Computer Science, Chemistry or related field.
• 5+ years’ experience in semiconductor photolithography or RET development.
• Lithography and RET expertise for the 45 nm, 28 nm, 22 nm and 20 nm technology nodes.
• Strong knowledge/understanding of advanced lithography processes, lithography simulation techniques, mask making and RET techniques used in semiconductor manufacturing and process development.

 

Preferred qualifications:

• Experience with PLRC and ORC.
• Familiarity with physical layout (OASIS, GDSII): viewing, measuring and manipulating it.
• Experience with code-version control, eg, Git.
• Demonstrated strong analytical and problem solving skills.
• Strong verbal and written communication skills. 
• Ability to work in teams and collaborate effectively with people in different functions. 
• Strong time management skills that enable on-time project delivery. 
• Demonstrated ability to build strong, influential relationships. 
• Ability to work effectively in a fast-paced and rapidly changing environment. 
• Ability to take the initiative and drive for results.