About Neurophos

The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.

Join us and shape the future of computing!

Location: Austin, TX

Reports To: Chief Technology Officer

FLSA Status: Exempt

Position Overview

We are seeking an exceptional Chief Engineer to own the technical execution of our first fully integrated prototype system. This system spans optical sources, electro-optic modulation, high-speed mixed-signal electronics, free-space optics, a programmable photonic compute element, and the firmware and host software that drive them. A mix of internal teams and external design partners develops each subsystem, and the prototype works only if all of them agree—numerically, electrically, optically, and mechanically—at every interface.

You will be the single technical authority who holds that agreement together. You will own the end-to-end system performance budget, maintain the architecture and interface definitions that all subsystems are built against, scrutinize the designs delivered by internal teams and vendors alike, and drive integration and bring-up in the laboratory. This is a hands-on engineering leadership role, not a program-management role: you will be expected to read a schematic and question a component choice, recompute a budget line and challenge a vendor's assumption, and trace a bring-up anomaly from a measured waveform back to the architectural decision that caused it.

Critically, the first successful demonstration marks the beginning of this role, not its end. The prototype is intended to live on as the company's permanent experimental platform for optical computing—the instrument on which we quantify how individual optical and electrical impairments propagate into end-to-end computational accuracy, and on which we prototype and evaluate alternative mathematical encodings of the core compute operation before committing them to silicon. You will own that platform for its full life: keeping it instrumented, reconfigurable, and trustworthy as a measurement reference, designing and running the experimental campaigns that answer the architecture questions for the next product generation, and ensuring that what we learn on the bench feeds directly into system models and design decisions.

If you have deep multi-disciplinary hardware intuition, the systems-engineering discipline to keep a complex program coherent, the technical credibility to hold both internal teams and external suppliers to a specification, and the experimental rigor to turn a laboratory system into a source of durable physical insight, this role will let you define whether a first-of-its-kind computing platform works—and what comes after it.

Primary Responsibilities

• System Performance Budget Ownership: Own, maintain, and defend the end-to-end system performance budget that flows top-level accuracy, signal-to-noise, and bandwidth requirements down into allocations for every subsystem. Keep the budget synchronized with the as-designed and as-measured hardware, identify the dominant performance-limiting elements, and drive the trade studies that resolve them.

• Architecture and Interface Control: Define and maintain the system architecture, requirements set, and interface definitions that every subsystem and supplier designs against. Ensure that electrical, optical, mechanical, thermal, and data interfaces are unambiguously specified, mutually consistent, and traceable to system-level requirements. Adjudicate interface conflicts and control changes as the design evolves.

• Technical Oversight of Suppliers and Design Partners: Serve as the technical counterpart to external design houses and component vendors. Review delivered schematics, layouts, bills of materials, component selections, and analysis packages; verify they meet specifications and stay within the system budget. Lead design reviews, drive resolution of findings, and recommend acceptance or rejection of deliverables.

• Hardware Design Review: Critically evaluate mixed-signal and high-speed electronic designs—drive and termination networks, data converter interfaces, transimpedance and amplification chains, power distribution, grounding, and signal integrity—as well as optical and opto-mechanical designs, for correctness, manufacturability, and margin. Identify errors and risks before they reach fabrication.

• Hardware–Software Alignment: Ensure firmware and host software meet hardware requirements and system-level use cases. Review control and data paths, register maps, timing and sequencing, calibration hooks, and test interfaces; hold the software effort accountable to the same specification and schedule discipline as the hardware.

• Integration, Bring-Up, and Validation: Plan and lead the integration sequence, define acceptance criteria at every subassembly boundary, and drive laboratory bring-up and debug of the assembled system. Correlate measured performance with predicted budgets, identify root causes of discrepancies, and feed results back into the architecture and model.

• Impairment Characterization and Experimental Campaigns: Design and execute controlled experiments on the demonstrated system to isolate and quantify the effect of individual optical and electrical impairments—noise, mismatch, nonlinearity, crosstalk, dispersion, drift, quantization, and timing error—on end-to-end computational accuracy. Deliberately inject, sweep, and stress impairments; separate correlated effects; and produce quantitative sensitivity results that establish which impairments actually govern system performance and which do not.

• Encoding and Architecture Experimentation: Support and enable experimentation with alternative mathematical encodings and signaling schemes at the core of the optical compute operation. Assess what each candidate encoding demands of the hardware, define the system changes needed to evaluate it, and turn measured results into architectural recommendations for subsequent product generations.

• Long-Lived Experimental Platform Stewardship: Own the prototype as a permanent, trustworthy measurement instrument well beyond the initial demonstration. Keep the system instrumented, reconfigurable, calibrated, and documented; maintain its measurement uncertainty budget so that results remain defensible; and evolve the hardware and software so new experiments can be run without rebuilding the platform.

Secondary Responsibilities

• Maintain the system requirements, verification and test matrices, and configuration-controlled documentation set that constitutes the program's plan of record, and extend it to cover the platform's experimental configurations.

• Own the technical risk register and open-item list; drive each item to a documented decision with a named owner and a closure date.

• Interface with the analog IC, digital design, photonic device, optics, and packaging teams to ensure subsystem-level design intent is faithfully represented at the system level, and to translate measured platform results into concrete design guidance.

• Partner with the system modeling and calibration teams to close the loop between prediction and measurement: supply validated parameters, design the experiments that discriminate between competing model hypotheses, and drive model refinement from measured data.

• Build and maintain the automated measurement, data capture, and analysis infrastructure that makes long-running experimental campaigns repeatable and their results archivable.

• Contribute to build planning, long-lead procurement decisions, test equipment definition, and schedule risk assessment for prototype builds.

• Mentor engineers across disciplines and raise the systems-engineering and experimental rigor of the broader organization.

Qualifications

• BS required; MS or PhD strongly preferred, in Electrical Engineering, Optical Engineering, Applied Physics, or a closely related field.

• 15+ years of professional experience developing complex multi-disciplinary hardware systems, including at least 3 years as the responsible system-level engineer or technical lead. Demonstrated ownership of at least one system carried from architecture definition through design, integration, laboratory bring-up, and subsequent experimental characterization.

• Proven ability to construct and maintain requirements sets, interface control documents, verification matrices, and quantitative performance budgets (link, noise, error, timing, or power budgets), and to flow top-level requirements down into defensible subsystem allocations.

• Demonstrated ability to design experiments that isolate a single physical mechanism within a system where multiple effects occur simultaneously. Comfort with measurement uncertainty, repeatability, confounding variables, and the discipline required to produce results that survive scrutiny. Familiarity with statistical design of experiments and sensitivity analysis.

• Strong working knowledge of analog and high-speed electronics—data-converter interfacing, transmission lines and termination, coupling and biasing, amplifier and detector front-ends, noise and distortion mechanisms, power integrity, and grounding. Must be able to independently review schematics and component selections and identify design errors.

• Deep understanding of the impairment mechanisms that limit real optical and mixed-signal systems—thermal, shot, and flicker noise; component mismatch; compression and harmonic distortion; bandwidth and group-delay limitations; crosstalk; quantization; jitter and drift—and the ability to predict their system-level consequences from first principles before measuring them.

• Solid understanding of optical system fundamentals—sources, fiber and free-space propagation, electro-optic modulation, photodetection, optical power budgets, and the coupling and alignment tolerances that govern real optical assemblies.

• Working fluency in linear algebra, signal processing, and modulation and encoding theory, sufficient to reason independently about alternative mathematical encodings of the compute operation and about what each one implies for hardware precision, dynamic range, and noise tolerance.

• Experience acting as the technical authority over external design houses, contract manufacturers, or component vendors, including specification writing, design review, deliverable acceptance, and technical negotiation.

• Sufficient understanding of embedded firmware, FPGA-based control, and host-side software architecture to specify, review, and challenge the software interfaces to the hardware. You do not need to write production firmware, but you must be able to tell when the software plan will not meet the system need.

• Strong proficiency in Python and/or MATLAB for performance budgeting, test automation, measurement data analysis, and system-level modeling.

• Excellent technical communication and documentation skills, and the credibility and temperament to make and defend architectural decisions across disciplines, with internal teams and external partners alike.

Preferred Skills

• Experience owning a laboratory testbed or experimental platform for multiple years, used by several teams to address successive research and architectural questions.

• Experience with high-channel-count systems in which many parallel electrical and optical channels must be matched, aligned, and calibrated.

• Familiarity with FPGA- or RFSoC-class platforms that integrate high-speed data converters and the board-level design practices associated with them.

• Experience with fiber-optic assemblies, connectorization and polish standards, optical alignment, and opto-mechanical tolerancing.

• Background in optical transceivers, coherent or direct-detection links, silicon photonics, or photonic computing platforms.

• Experience with modulation formats, coding, and precision–noise trade-offs in analog or optical computing, analog signal processing, or high-order signaling links.

• Familiarity with calibration architectures and their hardware and software implications at the system level.

• Experience with Monte Carlo analysis, error budgeting, and correlating behavioral system models with measured hardware.

• Experience running a formal gate review process (PDR/CDR-style) across internal teams and external suppliers.

• Familiarity with Cadence Virtuoso, Spectre, or comparable circuit simulation environments for independent verification of vendor analyses.

• Laboratory proficiency with high-speed oscilloscopes, network and spectrum analyzers, optical power meters, optical spectrum analyzers, and precision alignment equipment, including automated instrument control.

• Experience with configuration-controlled engineering documentation and issue tracking in a version-controlled environment.

What We Offer

This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on game-changing technology at the intersection of photonics and AI as part of a collaborative, brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.

 

Benefits

Join a team that invests in your future and your well-being. At Neurophos, we offer:

• 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.

• Unlimited PTO. No rigid vacation banks, just a focus on delivery.

• 401(k) matching and stock option opportunities to ensure our success is your success.

• Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.

• Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.