Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As physical design engineers as part on the CPU team, you will own CPU units for the full silicon development lifecycle.

THE ROLE

As a CPU Static Timing Analysis (STA) Engineer, you will participate in the following : 

• Responsible for performing timing and noise analysis on designs and rolling up analysis results. 

• Responsible for verifying the quality of the timing/noise runs and checking analysis coverage.

• Responsible for working with the design teams on understanding the violations and providing fixing suggestions/strategies as well as constraint refinements when needed.

• Responsible for performing ECO generation per design needs.

• Develop essential methodologies and infrastructure for Timing Analysis & Design closure.

• Responsible for working with the CAD team and providing feedbacks on tool/flow issues or enhancement requests to improve productivity. 

MINIMUM QUALIFICATIONS

• Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in static timing analysis on high-speed designs.

• Knowledge in industry-standard EDA tools and scripting languages.

• Understanding various timing and noise analysis checks and corresponding constraints.

• Strong communication and collaboration skills.

REQUIREMENTS — PREFERRED

• Possess substantial years of experience in CPU unit-level timing and noise analysis

• Understanding of timing noise models and hierarchical analysis strategies.. 

• Understanding of advanced technologies and scaling trends.

• Knowledge of physical design flow and methodology including logic synthesis, PnR, parasitic extraction, logic equivalence etc., which are related to timing analysis.

• Proficient in Python, Perl, or TCL to enhance design productivity and flow efficiency

• Experience in using Agentic AI tools for productivity and automation.